WUHAN, China (July 22, 2013) - Wuhan Optoelectronics Forum No. 74 was successfully held in Auditorium A101 at Wuhan National Laboratory for Optoelectronics (WNLO) in the morning of July 22.
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that possesses many attractive characteristics such as high density, low leakage and low read access latency. However, one of the major drawbacks of STT-RAM technology is its long write latency, which impedes its progress for wide spread adoption for on-chip caches compared to the traditional SRAM based caches. By adopting suitable mechanisms that can minimize the latency overhead of STT-RAM writes, it is possible to design energy-efficient and high density caches for CMPs. In this talk, I will discuss two complementary techniques to mitigate the write overhead of STT-RAM. The first approach centers on designing an elegant network level solution. This approach is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency.
While the first approach attempts to hide the STT-RAM write latency, our second approach focuses on reducing this write latency by tuning its data-retention time. We argue that by relaxing the non-volatility feature of STT-RAMs to have data-retention time in the range of milliseconds, we can optimize the on-chip cache architecture for CMPs. The advantages of both these techniques compared to the SRAM based cache architecture will be discussed.
Chita Das is a Distinguished Professor of Computer Science and Engineering at the Pennsylvania State University. His main areas of interest include CMPs and manycore architectures, performance evaluation, fault-tolerant computing, and Clouds/datacenters. In particular, he has worked extensively in the area of design and analysis of interconnection networks/on-chip interconnects. He has published more than 200 papers in the above areas, has received several best paper awards, and has served on many program committees, and editorial boards. He is a Fellow of the IEEE.
